MPRTA: An Efficient Multilevel Parallel Mobile Accelerator for High-Performance Ray Tracing

被引：0

作者：

Yan, Run ^{[1
,2
]}

Su, Yin ^{[1
,2
]}

Guo, Hui ^{[1
,2
]}

Lu, Yashuai ^{[3
]}

Wang, Jin ^{[1
,2
]}

Xiao, Nong ^{[1
,2
]}

Shen, Li ^{[1
,2
]}

Wang, Yongwen ^{[1
,2
]}

Huang, Libo ^{[1
,2
]}

机构：

[1] Natl Univ Def Technol, Sch Comp, Changsha 410005, Peoples R China

[2] Natl Univ Def Technol, Key Lab Adv Microprocessors Chips & Syst, Changsha 410005, Peoples R China

[3] Huawei2012 Labs, Beijing 100080, Peoples R China

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2024年 / 32卷 / 02期

基金：

中国国家自然科学基金;

关键词：

Computer architecture; computer graphics; domain-specific architecture; parallel; ray tracing; ARCHITECTURE;

D O I：

10.1109/TVLSI.2023.3334711

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Ray tracing has been regarded as the future of graphics rendering technology for a long time. However, interactive ray tracing still faces challenges, especially in mobile devices, such as high computational intensity and multiple branches. In this brief, we aim to maximize overall efficiency by leveraging all forms of potential parallelism, including task, basic block, loop, and pipeline levels. We present multilevel parallel ray tracing accelerator (MPRTA), an innovative mobile accelerator that offers high performance and optimal efficiency for ray tracing. Experimental results indicate that MPRTA is 1.67 x more efficient than the currently best-reported mobile accelerator.

引用

页码：396 / 400

页数：5

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