A 49-63 GHz Phase-locked FMCW Radar Transceiver for High Resolution Applications

被引：5

作者：

Liu, Xuyang ^{[1
]}

Maktoomi, Md Hedayatullah ^{[1
]}

Alesheikh, Mahdi ^{[1
]}

Heydari, Payam ^{[1
]}

Aghasi, Hamidreza ^{[1
]}

机构：

[1] Univ Calif Irvine, Dept Elect Engn & Comp Sci, Irvine, CA 92697 USA

来源：

IEEE 49TH EUROPEAN SOLID STATE CIRCUITS CONFERENCE, ESSCIRC 2023 | 2023年

关键词：

CMOS; FMCW radar; Coupled PLL; off-chip antenna; range resolution; stepped chirp radar;

D O I：

10.1109/ESSCIRC59616.2023.10268798

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents an mmWave FMCW radar that can achieve sub-centimeter-scale range resolution at 14-GHz chirp-bandwidth while maintaining the radar range beyond 50 meters. To meet the requirements on power efficiency, chirp linearity, and signal-to-noise ratio (SNR), a phase-locked stepped-chirp FMCW radar architecture is introduced. Specifically, a fully integrated radar transceiver comprising an interleaved frequency-segmented phase-locked transmitter and a segmented receiver architecture with high sensitivity is presented. The proposed design addresses the limitations of conventional type-II phase-locked loops (PLLs) in extending the radar bandwidth across multiple sub-bands with identical chirp profiles. Fabricated in a 22nm FD-SOI technology, the prototype chip comprises two sub-bands with 14 GHz of free-running bandwidth and 10 GHz of phase-locked bandwidth. The system achieves -101.7 dBc/Hz phase noise at 1 MHz offset, 8 dBm of effective isotropic radiated power (EIRP), 10 dB noise figure (NF), and 362.6 mW collective power consumption of transmitter and receiver arrays.

引用

页码：509 / 512

页数：4