Efficient Training Method for Memristor-Based Array Using 1T1M Synapse

被引：9

作者：

Feng, Renhai ^{[1
]}

Li, Jiahang ^{[1
]}

Xie, Sheng ^{[1
]}

Mao, Xurui ^{[2
]}

机构：

[1] Tianjin Univ, Sch Elect & Informat Engn, Tianjin 300072, Peoples R China

[2] Chinese Acad Sci, Inst Semicond, State Key Lab Integrated Optoelect, Beijing 100083, Peoples R China

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2023年 / 70卷 / 07期

关键词：

Memristor-based array; efficient training; 1T1M synapse; memristor; stochastic gradient descent; DESIGN; ARCHITECTURE; ENERGY; MODEL;

D O I：

10.1109/TCSII.2023.3241663

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this brief, an efficient training method for memristor-based array (crossbar) with one transistor and one memristor (1T1M) synapse is proposed, which enables parallel update of memristor-based arrays trained by stochastic gradient descent within two steps. Voltage ThrEshold Adaptive Memristor (VTEAM) model is utilized to describe memristor characteristics for simulations. On this basis, circuit parameters optimization method compensating the asymmetric and nonlinear weight update is provided for better training results. The effectiveness of proposed training method is evaluated on OR, AND functions and digit recognition task. Simulation results demonstrate the robustness of proposed training method to electrical noise and imperfections of memristors.

引用

页码：2410 / 2414

页数：5

共 22 条

[1] PANTHER: A Programmable Architecture for Neural Network Training Harnessing Energy-Efficient ReRAM [J].

Ankit, Aayush ;

El Hajj, Izzat ;

Chalamalasetti, Sai Rahul ;

Agarwal, Sapan ;

Marinella, Matthew ;

Foltin, Martin ;

Strachan, John Paul ;

Milojicic, Dejan ;

Hwu, Wen-Mei ;

Roy, Kaushik .

IEEE TRANSACTIONS ON COMPUTERS, 2020, 69 (08) :1128-1142

[2]

[Anonymous], 2015, Neural Networks (IJCNN), 2015 International Joint Conference on

[3]

Chanthbouala A, 2012, NAT MATER, V11, P860, DOI [10.1038/NMAT3415, 10.1038/nmat3415]

[4] MEMRISTIVE DEVICES AND SYSTEMS [J].

CHUA, LO ;

KANG, SM .

PROCEEDINGS OF THE IEEE, 1976, 64 (02) :209-223

[5] NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory [J].

Dong, Xiangyu ;

Xu, Cong ;

Xie, Yuan ;

Jouppi, Norman P. .

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2012, 31 (07) :994-1007

[6] A fast training method for memristor crossbar based multi-layer neural networks [J].

Hasan, Raqibul ;

Taha, Tarek M. ;

Yakopcic, Chris .

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2017, 93 (03) :443-454

[7] Learning in Memristive Neural Network Architectures Using Analog Backpropagation Circuits [J].

Krestinskaya, Olga ;

Salama, Khaled Nabil ;

James, Alex Pappachen .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2019, 66 (02) :719-732

[8] VTEAM: A General Model for Voltage-Controlled Memristors [J].

Kvatinsky, Shahar ;

Ramadan, Misbah ;

Friedman, Eby G. ;

Kolodny, Avinoam .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2015, 62 (08) :786-790

[9] Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies [J].

Kvatinsky, Shahar ;

Satat, Guy ;

Wald, Nimrod ;

Friedman, Eby G. ;

Kolodny, Avinoam ;

Weiser, Uri C. .

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2014, 22 (10) :2054-2066

[10] Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array [J].

Manem, Harika ;

Rajendran, Jeyavijayan ;

Rose, Garrett S. .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2012, 59 (05) :1051-1060

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