Performance Enhancement of Dual Material Gate Junctionless FinFETs using Dielectric Spacer

In this work, a detailed investigation is done on the effectiveness of various spacer materials having different spacer lengths (L-SP), in improving the performance of Dual-Material Gate-Junctionless FinFET (DMG-JLFinFET). Various performance metrics, such as Drain Induced Barrier Lowering (DIBL), Sub-threshold Swing (SS), ON current (I-ON), OFF current (I-OFF), ratio of I-ON to I-OFF (I-ON/I-OFF), and tunneling current (I-tunn), are closely monitored at gate lengths (L-g) down to 10 nm. DIBL degradation of 3.46 mV/V and SS degradation of 4.97 mV/dec are observed when L-g scales down from 30 nm to 10 nm. Except for the case of I-tunn, other performance metrics improve with an increase in dielectric constant and length of spacer materials. The optimum performance of DMG-JLFinFET with a channel length of 10 nm is obtained when L-SP is 5 nm. Enhancement in analog performance metrics is observed when high kappa materials are used as spacers. Transconductance Generation Factor (TGF) improves from 35.86 V(-1)( )to 47.4 V-1 and intrinsic gain increases from 6.93 dB to 11.98 dB when high kappa dielectric materials like TiO2 are incorporated as spacers in a DMG-JLFinFET.