FPGA-Based 8x8 Bits Signed Multipliers Using LUTs

Modern FPGAs (Field Programmable Gate Arrays) like Xilinx 7-series ones incorporate DSP blocks that contain 18x25 bits two's complement embedded multipliers. When FPGA-based small size signed multipliers are required, it is not practical to use these large size embedded multipliers. Thus, one can use LUTs (Look Up Tables) in FPGAs to implement them. Since the target signed multipliers are assumed in two's complement, a preprocessing is required for a LUT-based implementation. In this paper, Baugh-Wooley and sign-magnitude are used as preprocessing algorithms to realize two's complement 8x8 bits multipliers using LUTs in FPGAs. These two algorithms are used since they allow for a parallel realization of the signed multipliers. We synthesize 8x8 bits two's complements multipliers on LUTs using these two algorithms. As an application, we use the resulting synthesized designs to synthesize 8-taps and 16-taps digital Finite Impulse Response (FIR) filters for input data and coefficients in two's complement. Experimental results on Xilinx Artix-7 FPGAs using the Vivado 2020.2 synthesis tool show that the synthesized designs using the Baugh-Wooley algorithm are better in terms of speed and area compared to using the sign-magnitude.