Design and simulation of reconfigurable optical logic gates for integrated optical circuits

被引:10
作者
Soma, Savita [1 ]
Gowre, Sanjay Kumar C. [2 ]
Sonth, Mahesh V. [3 ]
Gadgay, Baswaraj [4 ]
Jyoti, B. [5 ]
机构
[1] Guru Nanak Dev Engn Coll, Dept Elect & Commun Engn, Bidar 585403, India
[2] Bheemanna Khandre Inst Technol, Bhalki 585328, India
[3] CMR Tech Campus, ECE Dept, Hyderabad 501401, India
[4] VTU Reg Off, Kalaburagi, Karnataka, India
[5] BKIT Bhalki, ECE Dept, Bidar, Karnataka, India
关键词
All optical logic gates; Cross-waveguides; Contrast ratio; 2D Photonic crystals; FDTD; PWE method; PHOTONIC CRYSTAL; REALIZATION; INTERFERENCE; OPTIMIZATION; NAND;
D O I
10.1007/s11082-022-04532-8
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The proposed work presents design and simulation of a new reconfigurable optical logic AND, NOT and NOR gate constructed in a two dimensional (2D) photonic crystals (PhCs). Due to many advantages like high speed, fast response, high bit rate and compact size these optical gates find applications in optical devices, communications and optical sensors for next generation optical systems. The proposed gate structures can be used in realization of all optical devices used in photonic integrated optical circuits. These optical logic gates are constructed in 6 mu m * 6 mu m in 2D PhCs square lattice structure with a lattice constant a = 0.648 mu m. All the gates are realized by creating structural disorders in the cross-waveguide geometries of 2D PhCs. The plane wave expansion (PWE) is utilised to get the complete band gap and required band of the waveguide. Finite difference time domain (FDTD) technique is utilised to investigate the performance of these gates. The several performance parameters are examined using this structure and observed that proposed structure has reduced size, fast response time, better contrast ratio against the existing designs and high bit rates of 1.88 Tbit/s and 1.55 Tbit/s for NOT and NOR gates respectively. The amplitude of the optical signal larger than 0.5 arbitrary units (a.u.) and less than 0.1 (a.u.) at output are considered as logic '1' and '0' respectively. The gates are implemented in third optical window at the wavelength of 1.55 mu m. RSoft FullWAVE simulator is used to perform simulation.
引用
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页数:12
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