This article introduces a novel debug unit enabling compositional postsilicon validation of heterogeneous SoCs. The unit's effectiveness is demonstrated in post-silicon validation by integrating it into a 12-nm complex SoC prototype. -Mahdi Nikdast, Colorado State University, USA -Miquel Moreto, Barcelona Supercomputing Center, Spain -Masoumeh (Azin) Ebrahimi, KTH Royal Institute of Technology, Sweden -Sujay Deb, IIIT Delhi, India