SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs

被引：0

作者：

Tombesi, Gabriele ^{[1
]}

Zuckerman, Joseph ^{[1
]}

Mantovani, Paolo ^{[1
]}

Giri, Davide ^{[1
]}

dos Santos, Maico Cassel ^{[1
]}

Jia, Tianyu ^{[2
]}

Brooks, David ^{[2
]}

Wei, Gu-Yeon ^{[2
]}

Carloni, Luca P. ^{[1
]}

机构：

[1] Columbia Univ, New York, NY 10027 USA

[2] Harvard Univ, Cambridge, MA 02138 USA

来源：

IEEE DESIGN & TEST | 2023年 / 40卷 / 06期

基金：

美国国家科学基金会;

关键词：

Registers; Pins; Computer architecture; Computer bugs; Software; Scalability; Prototypes; NETWORKS; DESIGN; REUSE;

D O I：

10.1109/MDAT.2023.3310355

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This article introduces a novel debug unit enabling compositional postsilicon validation of heterogeneous SoCs. The unit's effectiveness is demonstrated in post-silicon validation by integrating it into a 12-nm complex SoC prototype. -Mahdi Nikdast, Colorado State University, USA -Miquel Moreto, Barcelona Supercomputing Center, Spain -Masoumeh (Azin) Ebrahimi, KTH Royal Institute of Technology, Sweden -Sujay Deb, IIIT Delhi, India

引用

页码：64 / 75

页数：12

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