Study of the influence of virtual guard ring width on the performance of SPAD detectors in 180 nm standard CMOS technology

The influence of the virtual guard ring width (GRW) on the performance of the p-well/deep n-well single-photon avalanche diode (SPAD) in a 180 nm standard CMOS process was investigated. TCAD simulation demonstrates that the electric field strength and current density in the guard ring are obviously enhanced when GRW is decreased to 1 mu m. It is experimentally found that, compared with an SPAD with GRW = 2 mu m, the dark count rate (DCR) and afterpulsing probability (AP) of the SPAD with GRW = 1 mu m is significantly increased by 2.7 times and twofold, respectively, meanwhile, its photon detection probability (PDP) is saturated and hard to be promoted at over 2 V excess bias voltage. Although the fill factor (FF) can be enlarged by reducing GRW, the dark noise of devices is negatively affected due to the enhanced trap-assisted tunneling (TAT) effect in the 1 mu m guard ring region. By comparison, the SPAD with GRW = 2 mu m can achieve a better trade-off between the FF and noise performance. Our study provides a design guideline for guard rings to realize a low-noise SPAD for large-array applications.