共 11 条
[2]
Gitlin D, 2017, IEEE SOI3DSUB MICRO
[3]
Kim DH, 2009, IEEE INT INTERC TECH, P26, DOI 10.1109/IITC.2009.5090331
[4]
Die-to-die alignment for lithographic processing of reconstructed wafers
[J].
2022 SMART SYSTEMS INTEGRATION, SSI,
2022,
[6]
Mourier T, 2018, IEEE INT INTERC TECH, P141
[7]
Porous SiOCH integration: Etch challenges with a trench first metal hard mask approach
[J].
CHINA SEMICONDUCTOR TECHNOLOGY INTERNATIONAL CONFERENCE 2011 (CSTIC 2011),
2011, 34 (01)
:389-394
[9]
Suarez Berru J. J., 2023, IEEE 73 ELECT COMPON
[10]
Multi-tier N=4 Binary Stacking, combining Face-to-Face and Back-to-Back Hybrid Wafer-to-Wafer Bonding Technology
[J].
IEEE 71ST ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2021),
2021,
:1057-1062