An ultra-low quiescent current power-on reset circuit with DDPG method

被引：2

作者：

He, Luchang ^{[1
,2
]}

Wu, Qingyu ^{[2
]}

Xie, Chenchen ^{[2
]}

Li, Xi ^{[2
]}

Song, Zhitang ^{[2
]}

机构：

[1] Univ Sci & Technol China, Sch Microelect, Hefei 230026, Peoples R China

[2] Chinese Acad Sci, Shanghai Inst Microsyst & Informat Technol, Natl Key Lab Mat Integrated Circuits, Shanghai 200050, Peoples R China

来源：

AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS | 2024年 / 175卷

基金：

中国国家自然科学基金; 国家重点研发计划;

关键词：

Power-on reset; Reliability; Quiescent current; Pulse generation;

D O I：

10.1016/j.aeue.2023.155097

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An ultra -low quiescent current power -on reset (POR) circuit with double -delay pulse generation (DDPG) method is presented in this paper. The circuit is designed for non-volatile memory (NVM) systems, aiming to ensure reliable initialization and enhance overall efficiency. To address the challenge of inaccurate trigger-point voltage caused by process, voltage, temperature (PVT) and ramp time variations, a novel pulse generation method is proposed. Additionally, the circuit further improves the reliability of pulse duration through the utilization of low-cost current reference generators. Implemented in standard 40 nm CMOS technology, the delay -based POR circuit consumes only 0.24 nA quiescent current and occupies a compact area of 25.6 mu m x 102 mu m. The simulation results demonstrate a typical pulse duration time of 28 mu s, with a temperature coefficient (TC) of 101.4 ppm/C-o. The high reliability and low overhead of this circuit make it suitable for NVM systems and other fast power -on applications.

引用

页数：8

共 20 条

[1] Power-On Reset Circuit in 180-nm CMOS With Brownout Detection, Stable Switching Points, Long Reset Pulse Duration, and Resilience to Switching Noise [J].