SECALROC2: A Low-Noise, High-Speed, and Full Digital Outputs Front-End ASIC for STCF Electromagnetic Calorimeter With APD Detectors

被引:3
作者
Liu, Chao [1 ]
Zheng, Ran [1 ]
Wang, Jia [2 ]
Huang, Xuelei [1 ]
Zhao, Ziwei [1 ]
Xue, Feifei [1 ]
Wei, Xiaomin [1 ]
Hu, Yongcai [1 ]
机构
[1] Northwestern Polytech Univ, Inst Microelect, Sch Comp Sci & Technol, Xian 710072, Shaanxi, Peoples R China
[2] Northwestern Polytech Univ, Sch Elect & Informat, Xian 710072, Shaanxi, Peoples R China
基金
中国国家自然科学基金;
关键词
Avalanche photodiodes; Detectors; Delays; Analog-digital conversion; Registers; Energy measurement; Capacitance; Application-specific integrated circuit (ASIC); avalanche photodiode detector (APD); front-end readout; high capacitance detectors; high event rate; low noise; LOW-POWER; SAR ADC; READOUT; MULTICHANNEL; CONVERTER; RAY; OPTIMIZATION; CHANNEL; RANGE; TIME;
D O I
10.1109/TNS.2023.3238338
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this work, a low-noise and high-rate front-end readout application-specific integrated circuit (ASIC) named SECALROC2 for the electromagnetic calorimeter (ECAL) in the super tau-charm factory (STCF) is presented. The chip is designed to process signals generated from avalanche photodiode detectors (APDs) for both energy and time measurement. The large detector capacitance and leakage current of the APD pose a great challenge to the noise and speed performance of the front-end readout circuit (ROC). A low-noise preamplifier and a fifth-order high-linearity shaper with adjustable peaking times are proposed to decrease noise induced by the 270-pF detector capacitance. A peak detect-and-hold circuit and a high-linearity differential analog buffer are adopted to convert each peak voltage of the shaper to differential voltages with sufficient driving capability. A fast shaper and a discriminator are implemented to produce trigger signals for the time of arrival (TOA) measurement. To reduce the complexity and power consumption of the ECAL system, a 12-bit 10-MS/s pipelined analog-to-digital converter (ADC) and a 16-bit three-stage time-to-digital converter (TDC) with 42-ps bin size TDC are integrated on-chip for full-digitalized outputs. This ASIC was designed and fabricated in a standard commercial 1P6M 0.18-mu m mixed-signal CMOS process and the chip area occupancy is 2.4 x 1.6 mm(2). The experimental results show that the input charge of the ASIC ranges from 3.2 to 400 fC. The measured nonlinear error of the system is less than 2.5% with an event rate up to 400 kcps. The equivalent noise charge (ENC) is 1367 e(-) + 4.93 e(-)/pF at 800-ns peaking time. The timing resolution is better than 540 ps at an input charge of 160 fC. The measured ENC can achieve 3820 e(-) when the ASIC is connected to an APD detector. The effective number of bits (ENOB) of the ADC is 10.8-bit when operated at 10 MS/s.
引用
收藏
页码:139 / 149
页数:11
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