PowerSyn: A Logic Synthesis Framework With Early Power Optimization

Power is a great concern in integrated circuits (ICs) design flow, especially in portable devices. As an early stage in electronic design automation (EDA), logic synthesis can significantly affect the quality of the design. It is essential to optimize power in logic synthesis. However, logic synthesis only has a limited concern in power due to its inaccurate estimation. This is because critical physical information is missing at this stage. Furthermore, the empirical optimization sequences need enhancement, and they are not optimal for power, while optimizing power in the early stage is effective. Technology mapping can also improve power optimization with comprehensive power metrics in this sub-15 nm era. Therefore, we propose PowerSyn, a logic synthesis framework with early power optimization. It consists of a practical power model, a power-oriented logic optimization module, and a technology mapping stage. The power model leverages probability propagation considering glitches and static power. The acrlong RL-based logic optimization generates high-quality and rapid-convergence command sequence with early power optimization. We also modify traditional technology mapping with novel power-related metrics. We evaluate PowerSyn on the EPFL benchmark suite. Experiment results show that our flow achieves an average power savings of 16.1% compared to the state-of-the-art open-source logic optimization flow. It also delivers an 8.8% and a 2.1% reduction in latency and area, respectively. The flow incurs less than 12.2% execution time overhead during inference for command generation.