Integrated Photonic Tensor Processing Unit for a Matrix Multiply: A Review

被引:23
|
作者
Peserico, Nicola [1 ]
Shastri, Bhavin J. [2 ]
Sorger, Volker J. [3 ,4 ]
机构
[1] George Washington Univ, Dept Elect & Comp Engn, Washington, DC 20052 USA
[2] Queens Univ, Dept Phys Engn Phys & Astron, Kingston, ON K7L 3N6, Canada
[3] George Washington Univ, Dept Elect & Comp Engn, Washington, DC 20052 USA
[4] Optelligence LLC, Wilmington, DE 19801 USA
关键词
Matrix-vector multiplication; photonics; PICs; silicon photonics; tensor core; CONVOLUTIONAL NEURAL-NETWORKS; SILICON; COMPRESSION; MODULATOR; CIRCUITS; DESIGN; OPTICS;
D O I
10.1109/JLT.2023.3269957
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The explosion of artificial intelligence and machine-learning algorithms, connected to the exponential growth of the exchanged data, is driving a search for novel application-specific hardware accelerators. Among the many, the photonics field appears to be in the perfect spotlight for this global data explosion, thanks to its almost infinite bandwidth capacity associated with limited energy consumption. In this review, we will overview the major advantages that photonics has over electronics for hardware accelerators, followed by a comparison between the major architectures implemented on Photonics Integrated Circuits (PIC) for both the linear and nonlinear parts of Neural Networks. By the end, we will highlight the main driving forces for the next generation of photonic accelerators, as well as the main limits that must be overcome.
引用
收藏
页码:3704 / 3716
页数:13
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