Performance verification and latency time evaluation of hardware image processing module for appearance inspection systems using FPGA

This paper analyzes a hardware-accelerated image processing module for visual inspection systems. These systems are essential for maintaining product quality and decreasing manual inspection. The proposed system harnesses FPGA technology to enhance the efficiency of image processing tasks, with a specific focus on filtering and labeling processes. To evaluate the performance gains achieved through hardware processing, the latency metric is put to use, which holds significant importance in real-time applications. The FPGA-based hardware processing methods have been shown to be highly effective in enhancing the performance of visual inspection systems. The experimental results prove that these methods successfully reduce latency up to the microsecond level, resulting in remarkable improvements in overall system performance. On average, the FPGA-based solution is demonstrated to be 10-100 times faster than conventional processors. Additionally, a notable advantage of this approach is its ability to synchronize processing with the inspection target flow, leveraging the camera device and sensor timing.