Performance limit of one-dimensional SbSI nanowire transistors

被引:1
作者
Tan, Xingyi [1 ,2 ]
Li, Qiang [2 ]
Ren, Dahua [2 ]
机构
[1] Chongqing Three Gorges Univ, Dept Phys, Wanzhou 404100, Peoples R China
[2] Hubei Minzu Univ, Coll Intelligent Syst Sci & Engn, Enshi 445000, Peoples R China
基金
中国国家自然科学基金;
关键词
MOS2; TRANSISTORS; GATE;
D O I
10.1039/d3tc00517h
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
It has been suggested that low-dimensional materials can substitute for silicon-based materials to get around the scaling issues in existing field-effect transistors (FETs). The current study is based on the simulation of gate-all-around (GAA) SbSI nanowire FETs by making use of the ab initio quantum transport technique. The simulated results manifest gate-length (L-g, L-g = 5, 3, 1 nm) n- and p-type GAA SbSI FETs with a suitable underlap that is able to fulfill the power dissipation, delay time, and on-state current for the 2028 prerequisites for the high-performance and low-dissipation requirements of the International Technology Roadmap for Semiconductors (ITRS) of 2013. As a result, GAA SbSI FETs may be a viable option for scaling Moore's law to 1 nm.
引用
收藏
页码:5779 / 5787
页数:9
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