Comprehensive Analysis of a Power-Efficient 1-Bit Hybrid Full Adder Cell

There is an intensive demand for energy-efficient computing gadgets. To optimize the arithmetic unit of these devices, this paper presents a 1-bit full adder cell designed using a hybrid logic scheme. The reported cell employs 18-transistors and performs better than existing hybrid full adder cells, while maintaining full swing output and minimum chip-area. The layout design simulation is performed on 65 nm, 45 nm and 32 nm technology nodes. The power consumption, delay and power-delay product are reduced by 20%, 36.45% and 40.13%, respectively as compared to the earlier reported hybrid full adder circuits. In addition, the layout area is improved up to 41.32%. The improved performance of the proposed hybrid full adder cell is validated at different voltages and temperatures.