ADC Architectural Study for Digitally-Assisted Multi-Gigabit Data Communication Transceivers

被引：0

作者：

Barba, Pedro ^{[1
]}

Rodriguez-Perez, Alberto ^{[1
]}

Prefasi, Enrique ^{[1
]}

del Rio, Rocio ^{[2
]}

Guerra, Oscar ^{[2
]}

机构：

[1] KDROC, R&D Dept, Madrid, Spain

[2] US, CSIC, Inst Microelect Sevilla, Seville, Spain

来源：

2023 38TH CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS, DCIS | 2023年

关键词：

ADCs; high-speed communications; time interleaving; metastability; design methodologies; behavioral models; asynchronous SAR; SAR ADC; SPEED;

D O I：

10.1109/DCIS58620.2023.10335974

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a methodology for comparing both SAR and pipeline-SAR ADC architectures based on a target ENOB. First, a system-level model is used to select the parameters needed to achieve a given ENOB. Then, the power consumption of the solution is estimated. Finally, the different architectures are compared based on that estimation. A sample rate of 25GHz, 7 bits of ENOB and a metastability probability of 10-12 have been used as a reference considering the requirement for a PAM-4, 25Gbps ADC-based transceiver. A design space for these specifications has been obtained.

引用

页数：5

共 11 条

[1] A 13b 600-675MS/s Tri-State Pipelined-SAR ADC With Inverter-Based Open-Loop Residue Amplifier
Guo, Xiaofeng
Chen, Run
Chen, Zhenqi
Li, Bin
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2023, 58 (03) : 624 - 633
[2] Merged capacitor switching based SAR ADC with highest switching energy-efficiency
Hariprasath, V.
Guerber, J.
Lee, S. -H.
Moon, U. -K.
[J]. ELECTRONICS LETTERS, 2010, 46 (09) : 620 - U35
[3] A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS
Kull, Lukas
Toifl, Thomas
Schmatz, Martin
Francese, Pier Andrea
Menolfi, Christian
Braendli, Matthias
Kossel, Marcel
Morf, Thomas
Andersen, Toke Meyer
Leblebici, Yusuf
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2013, 48 (12) : 3049 - 3058
[4] A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS
Liang, Yuhua
Zhu, Zhangming
Ding, Ruixue
[J]. MICROELECTRONICS JOURNAL, 2015, 46 (10) : 988 - 995
[5] Limits on ADC power dissipation
Murmann, B
[J]. ANALOG CIRCUIT DESIGN: RF CIRCUITS: WIDE BAND, FRONT-ENDS,DAC'S, DESIGN METHODOLOGY AND VERIFICATION FOR RF AND MIXED-SIGNAL SYSTEMS, LOW POWER AND LOW VOLTAGE, 2006, : 351 - 367
[6] CMOS ADC-Based Receivers for High-Speed Electrical and Optical Links
Palermo, Samuel
Hoyos, Sebastian
Shafik, Ayman
Tabasy, Ehsan Zhian
Cai, Shengchang
Kiran, Shiva
Lee, Keytaek
[J]. IEEE COMMUNICATIONS MAGAZINE, 2016, 54 (10) : 168 - 175
[7] In the Pursuit of the Optimal Accuracy-Speed-Power Analog-to-Digital Converter Architecture: A mathematical framework
Ramkaj A.
Pelgrom M.J.M.
Steyaert M.S.J.
Tavernier F.
[J]. IEEE Solid-State Circuits Magazine, 2022, 14 (01): : 45 - 53
[8] Yield and speed optimization of a latch-type voltage sense amplifier
Wicht, B
Nirschl, T
Schmitt-Landsiedel, D
[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (07) : 1148 - 1158
[9] Part II: Asynchronous
Yu A.
Bankman D.
Zheng K.
Murmann B.
[J]. IEEE Solid-State Circuits Magazine, 2019, 11 (03): : 16 - 32
[10] Yueksel H, 2015, PROC EUR SOLID-STATE, P148, DOI 10.1109/ESSCIRC.2015.7313850

← 1 2 →