FPGA implementation of robust and low complexity template-based watermarking for digital images

Watermarking is a widespread technique for information protection and an invisible alternative to quick response codes. The literature mainly considers software implementations of watermarking methods, even though there are applications for which hardware watermarking solutions become preferable or the only possible option due to increased speed, power, or information safety requirements. A convenient, flexible, and universal solution for hardware development is intellectual property (IP) cores. IP cores are building blocks for creating processors on FPGA or ASIC. The main objective of this work is to present the implementation of the robust watermarking method in the form of an IP core suitable for image processing systems on processors. The main contribution of this work is that it is the first hardware implementation of template-based watermarking for modern neural network-based extraction methods. The paper briefly discusses the existing hardware solutions for embedding data, describes the implemented watermarking method and the implementation itself, and provides the key indicators of the resulting solution and a link to the public repository with the solution. The proposed watermarking scheme has good imperceptibility (PSNR of 39.66), bpp of 0.00097, and BER of less than 3% for attacks. The implementation supports a frequency of 120 MHz.