ImaGen: A General Framework for Generating Memory- and Power-Efficient Image Processing Accelerators

被引:6
作者
Ujjainkar, Nisarg [1 ]
Leng, Jingwen [2 ]
Zhu, Yuhao [1 ]
机构
[1] Univ Rochester, Rochester, NY 14627 USA
[2] Shanghai Jiao Tong Univ, Shanghai, Peoples R China
来源
PROCEEDINGS OF THE 2023 THE 50TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, ISCA 2023 | 2023年
关键词
Accelerator; Line Buffer; Image Processing; Constrained Optimization; Synthesis; Compiler; LANGUAGE; COMPILER;
D O I
10.1145/3579371.3589076
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Image processing algorithms are prime targets for hardware acceleration as they are commonly used in resource- and power-limited applications. Today's image processing accelerator designs make rigid assumptions about the algorithm structures and/or on-chip memory resources. As a result, they either have narrowapplicability or result in inefficient designs. This paper presents a compiler framework that automatically generates memory- and power-efficient image processing accelerators. We allow programmers to describe generic image processing algorithms (in a domain specific language) and specify on-chip memory structures available. Our framework then formulates a constrained optimization problem that minimizes on-chip memory usage while maintaining theoretical maximum throughput. The key challenge we address is to analytically express the throughput bottleneck, on-chip memory contention, to enable a lightweight compilation. FPGA prototyping and ASIC synthesis show that, compared to existing approaches, accelerators generated by our framework reduce the on-chip memory usage and/or power consumption by double digits. ImaGen code is available at: https://github.com/horizon-research/imagen.
引用
收藏
页码:579 / 591
页数:13
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