A 10-bit 10 MS/s SAR ADC with Duty-Cycled Multiple Feedback Filter

This paper presents a co-design of a 10-bit SAR ADC and its front-end filter. Because the SAR ADC works as a discrete-time data converter, its input signal only needs to be accurate at its sampling moment. Therefore, the filter can be switched off in the ADC conversion phase to save power. To reduce the start-up time when the filter is activated again, a low-power auxiliary amplifier is used in the ADC conversion phase to maintain the filter output roughly. A 10-bit 10 MS/s SAR ADC with such a duty-cycled multiple feedback filter is fabricated in a 65 nm CMOS technology. The filter power has been reduced by 36% thanks to the proposed duty-cycled operation. The prototype achieves 8.3 ENOB and 59.3 dB SFDR at low input frequencies, and it has 40 dB suppression at the Nyquist input frequency, while consuming 91.1 mu W.