A 9-bit 8.3 MS/s column SAR ADC with hybrid RC DAC for CMOS image sensors

This paper presents a synchronous 9-bit column successive approximation register (SAR) ADC for CMOS imaging sensors. The SAR ADC uses a pseudo-differential RC DAC and a split capacitor array to reduce power consumption and chip area. To improve the sampling rate and accuracy of the column ADC, a dynamic comparator consisting of a two-stage preamplifier and a latch, as well as the output offset storage (OOS) technique is adopted. Based on a 180 nm standard CMOS technology, the presented SAR ADC was taped out and verified. The test results show that the designed SAR ADC achieves the SFDR of 64.54 dB, the ENOB of 8.35 bits, and a power consumption of 0.5 mW with FOM of 235 fJ/conversion-step at 8.3 MS/s sample rate under 1.8 V power supply. The proposed SAR ADC is very suitable for the readout circuit interface of large-scale imaging sensors.