A latch-based sense amplifier with improved performance for single ended SRAM application

The growing processing load and decreasing technology node has augmented the need for single ended memory. Consequently, generating requirement for a single ended sense amplifier for ease of integration with single ended memory. Therefore, this paper presents a single bitline based latch type sense amplifier. It is designed at feature size of 32 nm and its performance is evaluated at 1 V supply, with the environment temperature at 27 degrees C. It is analyzed for its output waveform, delay, variability tolerance, and area occupancy. The ON current for the proposed sense amplifier is 1.2 uA, while the OFF current is 10 nA. The ON current for proposed sense amplifier is 0.18, 0.43, and 0.88 times higher than SA-2, SA-5, and SA-6 respectively. While, its OFF current is lowest with the exception of SA-3 at 9 nA. Also, the delay for the proposed sense amplifier is minimal at 0.77 ns in comparison to other topologies. The SA-1, SA-2, SA-5, and SA-6 are 3.9, 2.8, 3.7, and 0.3 times slower than SA-P, thereby deeming its operation faster than others. The reliability for the proposed circuit is evaluated using process corner analysis for all performance parameters.