HeterGenMap: An Evolutionary Mapping Framework for Heterogeneous NoC-Based Neuromorphic Systems

被引:0
作者
Dang, Khanh N. [1 ]
Doan, Nguyen Anh Vu [2 ]
Nguyen, Ngo-Doanh [1 ]
Abdallah, Abderazek Ben [1 ]
机构
[1] Univ Aizu, Grad Sch Comp Sci & Engn, Aizu Wakamatsu, Fukushima 9658580, Japan
[2] Infineon Technol AG, D-85579 Munich, Germany
关键词
Neural networks; Neuromorphics; Genetic algorithms; Task analysis; Routing; Hardware; Synapses; Fault tolerance; Network-on-chip; Fault-tolerance; spiking neural network; neuromorphic system; network-on-chip; max flow; migration; SPIKING NEURAL-NETWORKS;
D O I
10.1109/ACCESS.2023.3345168
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
While task mapping for multi-core systems is known as an NP-hard problem, mapping for neuromorphic systems even scale it up due to a high number of neurons per core and a high number of core per system. Moreover, mapping for neuromorphic systems also has several challenges such as heterogeneous computing core or communication fabrics, and potential defects in neurons or routing units. Therefore, this paper presents a genetic algorithm framework named HeterGenMap which is a Genetic Algorithm framework for mapping multiple-layer Spiking Neural Network systems to solve the aforementioned problems. The results show that HeterGenMap improves the overall communication cost by 11.04-26.77% in comparison to the linear mapping. Moreover, under link faulty scenarios, neuron defects, or multi-chip designs, HeterGenMap can reduce the communication cost by 3.41-31.34%, 7.01%-41.51%, and 34.21-45.56% in comparison to the linear approach, respectively. The validation in hardware also demonstrated that HeterGenMap reduces the inference time by 63.10-77.87% from the linear mapping.
引用
收藏
页码:144095 / 144112
页数:18
相关论文
共 39 条
[1]   True North: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip [J].
Akopyan, Filipp ;
Sawada, Jun ;
Cassidy, Andrew ;
Alvarez-Icaza, Rodrigo ;
Arthur, John ;
Merolla, Paul ;
Imam, Nabil ;
Nakamura, Yutaka ;
Datta, Pallab ;
Nam, Gi-Joon ;
Taba, Brian ;
Beakes, Michael ;
Brezzo, Bernard ;
Kuang, Jente B. ;
Manohar, Rajit ;
Risk, William P. ;
Jackson, Bryan ;
Modha, Dharmendra S. .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2015, 34 (10) :1537-1557
[2]   Hyperdrive: A Multi-Chip Systolically Scalable Binary-Weight CNN Inference Engine [J].
Andri, Renzo ;
Cavigelli, Lukas ;
Rossi, Davide ;
Benini, Luca .
IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, 2019, 9 (02) :309-322
[3]  
Balaji A., 2023, IEEE Trans. Emerg. Topics Comput., V11
[4]   Mapping Spiking Neural Networks to Neuromorphic Hardware [J].
Balaji, Adarsha ;
Das, Anup ;
Wu, Yuefeng ;
Huynh, Khanh ;
Dell'Anna, Francesco G. ;
Indiveri, Giacomo ;
Krichmar, Jeffrey L. ;
Dutt, Nikil D. ;
Schaafsma, Siebren ;
Catthoor, Francky .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2020, 28 (01) :76-86
[5]   Toward Robust Cognitive 3D Brain-Inspired Cross-Paradigm System [J].
Ben Abdallah, Abderazek ;
Dang, Khanh N. .
FRONTIERS IN NEUROSCIENCE, 2021, 15
[6]   Neurogrid: A Mixed-Analog-Digital Multichip System for Large-Scale Neural Simulations [J].
Benjamin, Ben Varkey ;
Gao, Peiran ;
McQuinn, Emmett ;
Choudhary, Swadesh ;
Chandrasekaran, Anand R. ;
Bussat, Jean-Marie ;
Alvarez-Icaza, Rodrigo ;
Arthur, John V. ;
Merolla, Paul A. ;
Boahen, Kwabena .
PROCEEDINGS OF THE IEEE, 2014, 102 (05) :699-716
[7]   Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement [J].
Bhanu, P. Veda ;
Kulkarni, Pranav Venkatesh ;
Soumya, J. .
ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 2019, 15 (01)
[8]   Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations [J].
Carrillo, Snaider ;
Harkin, Jim ;
McDaid, Liam J. ;
Morgan, Fearghal ;
Pande, Sandeep ;
Cawley, Seamus ;
McGinley, Brian .
IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2013, 24 (12) :2451-2461
[9]   RAMAN: Reinforcement Learning Inspired Algorithm for Mapping Applications onto Mesh Network-on-Chip [J].
Choudhary, Jitesh ;
Soumya, J. ;
Cenkeramaddi, Linga Reddy .
2021 ACM/IEEE INTERNATIONAL WORKSHOP ON SYSTEM-LEVEL INTERCONNECT PATHFINDING (SLIP 2021), 2021, :52-58
[10]   MigSpike: A Migration Based Algorithms and Architecture for Scalable Robust Neuromorphic Systems [J].
Dang, Khanh N. ;
Nguyen Anh Vu Doan ;
Ben Abdallah, Abderazek .
IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING, 2022, 10 (02) :602-617