Improved SOI FinFETs Performance With Low-Temperature Deuterium Annealing

Low-temperature deuterium annealing (LTDA) was applied to a silicon-on-insulator (SOI) n-channel FinFET to improve device performance and reliability. LTDA at 300 degrees C, which is roughly 100 degrees C lower than a conventional forming gas annealing (FGA) process with hydrogen, is attractive to reduce the thermal budget. To confirm improved performance, the ON-state current (I-on), OFF-state current (I-off), subthreshold swing (SS), trans-conductance (gm), and gate leakage current (I-G) were evaluated. Thereafter, the parasitic sheet resistance (R-poly,R-sheet) of gate was characterized and compared between before and after LTDA. The decreased R-poly,R-sheet induced by LTDA is attractive for reducing RC delay. In a reliability point of view, damaged device characteristics by intentional hot-carrier injection (HCI) were recovered by LTDA. In addition to electrical analyses of LTDA effects, deuterium to form the Si-D bonds at the Si channel interface was physically mapped along the perpendicular direction to a FinFET by using time-of-flight secondary-ion mass spectrometry (ToF-SIMS).