Electrical characterization of SOI pMOS device leakage

被引：2

作者：

Bosch, D. ^{[1
]}

Lheritier, P. ^{[1
]}

Guyader, F. ^{[2
]}

Joblot, S. ^{[2
]}

Ponthenier, F. ^{[1
]}

Lacord, J. ^{[1
]}

机构：

[1] Univ Grenoble Alpes, CEA, Leti, F-38000 Grenoble, France

[2] STMicroelect, 850 Rue Jean Monnet, F-38926 Crolles, France

来源：

SOLID-STATE ELECTRONICS | 2023年 / 208卷

关键词：

pMOS SOI; Drain leakage; GIDL; SRH; MODEL; GIDL;

D O I：

10.1016/j.sse.2023.108740

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This work investigates Silicon-on-Insulator (SOI) pMOS leakage current. Temperature measurements indicates the superposition of two leakage mechanisms: band-to-band tunneling (BTBT) and Shockley-Read-Hall FieldEnhanced (SRHFE) generation recombination. Thanks to a dedicated low current measurement setup, the impact of device width (W), thickness (tsi) and polarization (back bias, drain and source) on leakage level is evaluated for both mechanisms.

引用

页数：4

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