An Equivalence Checking Framework for Agile Hardware Design

被引:0
作者
Wang, Yanzhao [1 ]
Xie, Fei [1 ]
Yang, Zhenkun [2 ]
Cocchini, Pasquale [2 ]
Yang, Jin [2 ]
机构
[1] Portland State Univ, Dept Comp Sci, Portland, OR 97229 USA
[2] Intel Corp, Strateg CAD Labs, Hillsboro, OR 97124 USA
来源
2023 28TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC | 2023年
关键词
Equivalence Checking; Halide; Agile Hardware; Formal Verification;
D O I
10.1145/3566097.3567843
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Agile hardware design enables designers to produce new design iterations efficiently. Equivalence checking is critical in ensuring that a new design iteration conforms to its specification. In this paper, we introduce an equivalence checking framework for hardware designs represented in HalideIR. HalideIR is a popular intermediate representation in software domains such as deep learning and image processing, and it is increasingly utilized in agile hardware design. We have developed a fully automatic equivalence checkingworkflow seamlessly integrated with HalideIR and several optimizations that leverage the incremental nature of agile hardware design to scale equivalence checking. Evaluations of two deep learning accelerator designs show our automatic equivalence checking framework scales to hardware designs of practical sizes and detects inconsistencies that manually crafted tests have missed.
引用
收藏
页码:26 / 32
页数:7
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