50-GFLOPS Floating-Point Adder and Multiplier Using Gate-Level-Pipelined Single-Flux-Quantum Logic With Frequency-Increased Clock Distribution

被引:3
作者
Nagaoka, Ikki [1 ]
Kashima, Ryota [1 ,2 ]
Tanaka, Masamitsu [1 ]
Kawakami, Satoshi [3 ]
Tanimoto, Teruo [3 ]
Yamashita, Taro [1 ,4 ]
Inoue, Koji [3 ]
Fujimaki, Akira [1 ]
机构
[1] Nagoya Univ, Nagoya 4648603, Japan
[2] Toyota Ind Corp, Kariya 4488671, Japan
[3] Kyushu Univ, Fukuoka 8190395, Japan
[4] Tohoku Univ, Sendai 9808579, Japan
关键词
Adders; Logic gates; Clocks; Pipeline processing; Throughput; Pipelines; Synchronization; Clock distribution; floating-point adder; floating-point multiplier; gate-level pipelining; SFQ logic; DESIGN;
D O I
10.1109/TASC.2023.3250614
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We demonstrate the functioning of a high throughput, gate-level-pipelined floating-point adder and multiplier over 50 GHz. The gate-level-pipelined floating-point adder and multiplier requires dedicated circuit blocks to wait until other circuit blocks complete calculations because of the dependence between their sign, exponent, and significand parts. We revealed that the resultant delay difference of the waiting circuit blocks hinders high-frequency operation if the predesigned circuit blocks with the fixed clock distribution are connected in a simple manner. We showed that clock distribution needs to synchronize with every pipeline stage regardless of the circuit blocks to minimize the delay difference between the circuit blocks for circuits containing the waiting circuit blocks (e.g., the floating-point adder and multiplier). We designed a 5-bit floating-point adder and multiplier to demonstrate the effectiveness of the clock distribution experimentally. The test chips were fabricated using AIST 10-kA/cm(2) Advanced Process 2. We verified the high-speed operation at over 50 GHz in the floating-point adder and multiplier. The maximum clock frequency and throughput of the floating-point adder were 56 GHz and 56 GFLOPS, respectively. The corresponding values for the floating-point multiplier were 63 GHz and 63 GFLOPS, respectively.
引用
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页数:11
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