A Unioned Graph Neural Network Based Hardware Trojan Node Detection

被引:0
作者
Pan, Weitao [1 ]
Dong, Meng [1 ]
Wen, Cong [2 ]
Liu, Hongjin [3 ]
Zhang, Shaolin [3 ]
Shi, Bo [3 ]
Di, Zhixiong [4 ]
Qiu, Zhiliang [1 ]
Gao, Yiming [1 ]
Zheng, Ling [5 ]
机构
[1] Xidian Univ, State Key Lab Integrated Serv Networks, Xian 710071, Peoples R China
[2] Xidian Univ, Sch Microelect, Xian 710071, Peoples R China
[3] Beijing Sunwise Space Technol Ltd, Beijing 100010, Peoples R China
[4] Southwest Jiaotong Univ, Sch Informat Sci & Technol, Chengdu, Peoples R China
[5] Xian Univ Posts & Telecommun, Sch Commun & Informat Engn, Xian, Peoples R China
关键词
Hardware Trojan Detection; Graph Neural Network; Golden Reference-Free; Gate-Level Netlist; CENTRALITY;
D O I
10.1587/elex.2.230204
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The globalization of the integrated circuit (IC) industry has raised concerns about hardware Trojans (HT), and there is an urgent need for efficient HT-detection methods of gate-level netlists. In this work, we propose an approach to detect Trojan-nodes at the gate level, based on graph learning. The proposed method does not require any golden model and can be easily integrated into the integrated circuits design flow. In addition, we further design a unioned GNN network to combine information from the input side, output side, and neighbor side of the directed graph to generate representative node embeddings. The experimental results show that it could achieve 93.4% in recall, 91.4% in F-measure, and 90.7% in precision on average across different designs, which outperforms the state-of-the-art HT detection methods.
引用
收藏
页数:6
相关论文
共 32 条
[1]  
Acharya A, 2009, INT CONF PERVAS COMP, P11
[2]   On Reverse Engineering-Based Hardware Trojan Detection [J].
Bao, Chongxi ;
Forte, Domenic ;
Srivastava, Ankur .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2016, 35 (01) :49-57
[3]  
Bhunia S., 2017, The Hardware Trojan War: Attacks, Myths, and Defenses, V1st, DOI DOI 10.1007/978-3-319-68511-3
[4]   On variants of shortest-path betweenness centrality and their generic computation [J].
Brandes, Ulrik .
SOCIAL NETWORKS, 2008, 30 (02) :136-145
[5]  
Goldstein L. H., 1980, Proceedings of the 17th Design Automation Conference, P190, DOI 10.1145/800139.804528
[6]   Pre-Silicon Security Verification and Validation: A Formal Perspective [J].
Guo, Xiaolong ;
Dutta, Raj Gautam ;
Jin, Yier ;
Farahmandi, Farimah ;
Mishra, Prabhat .
2015 52ND ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2015,
[7]  
Hamilton W.L., 2020, Synthesis Lectures on Artifical Intelligence and Machine Learning, V14, P1, DOI DOI 10.2200/S01045ED1V01Y202009AIM046
[8]  
Hamilton WL, 2017, ADV NEUR IN, V30
[9]  
Hasegawa K, 2022, Arxiv, DOI arXiv:2112.02213
[10]  
Hasegawa K, 2017, IEEE INT SYMP CIRC S, P2154