A 4.5 μW Miniaturized 3-Channel Wireless Intra-Cardiac Acquisition System

被引:1
|
作者
Rezaeiyan, Yasser [1 ]
Koolivand, Yarallah [2 ]
Zamani, Milad [1 ]
Shoaei, Omid [3 ]
Akbari, Meysam [4 ]
Moradi, Farshad [1 ]
Tang, Kea-Tiong [5 ]
机构
[1] Aarhus Univ, Dept Engn, Integrated Circuits & Elect Lab, DK-8200 Aarhus, Denmark
[2] KN Toosi Univ Technol, Elect Engn, Tehran 1541849611, Iran
[3] Univ Tehran, Sch Elect & Comp Engn, Biointegrated Syst Lab, Tehran 1439957131, Iran
[4] Univ Kurdistan, Dept Elect Engn, Sanandaj 6617715175, Iran
[5] Natl Tsing Hua Univ, Dept Elect Engn, Hsinchu 30013, Taiwan
关键词
Monitoring; Modulation; Electrocardiography; Frequency modulation; Wireless communication; Transmitters; Receivers; Analog front-end (AFE); electrocardiography (ECG); intra-cardiac signal; implantable systems; wireless telemetry; FRONT-END; CHOPPER AMPLIFIER; DYNAMIC-RANGE; MODE; SOC; EXTRACTION; TOLERANT; SENSOR; ADC;
D O I
10.1109/TBCAS.2023.3294560
中图分类号
R318 [生物医学工程];
学科分类号
0831 ;
摘要
This article presents a chip designed for wireless intra-cardiac monitoring systems. The design consists of a three-channel analog front-end, a pulse-width modulator featuring output-frequency offset and temperature calibration, and inductive data telemetry. By employing a resistance boosting technique in the instrumentation amplifier feedback, the pseudo-resistor exhibits lower non-linearity, leading to a total harmonic distortion of below 0.1%. Furthermore, the boosting technique enhances the feedback resistance, leading to a reduction in the size of the feedback capacitor and, consequently, the overall size. To make the modulator's output frequency resilient to temperature and process changes, coarse and fine-tuning algorithms are used. The front-end channel is capable of extracting the intra-cardiac signal with an effective number of bits of 8.9, while exhibiting an input-referred noise of less than 2.7 mu V-rms , and consuming 200 nW per channel. The front-end output is encoded by an ASK-PWM modulator, which drives an on-chip transmitter at 13.56 MHz. The proposed System-on-Chip (SoC) is fabricated in a 0.18 mu m standard CMOS technology and consumes 4.5 mu W while occupying 1.125 mm(2) .
引用
收藏
页码:1097 / 1110
页数:14
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