Compositional verification of embedded real-time systems

被引:4
作者
Foughali, Mohammed [1 ]
Hladik, Pierre-Emmanuel [2 ]
Zuepke, Alexander [3 ]
机构
[1] Univ Paris Cite, CNRS, IRIF, F-75013 Paris, France
[2] Nantes Univ, CNRS, LS2N, F-44000 Nantes, France
[3] Tech Univ Munich, D-85748 Garching, Germany
关键词
Formal methods; Real-time systems; Timed automata; Integer linear programming; FORMAL VERIFICATION; MODEL-CHECKING; SYNCHRONIZATION;
D O I
10.1016/j.sysarc.2023.102928
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In an embedded real-time system (ERTS), real-time tasks (software) are typically executed on a multicore shared-memory platform (hardware). The number of cores is usually small, contrasted with a larger number of complex tasks that share data to collaborate. Since most ERTSs are safety-critical, it is crucial to rigorously verify their software against various real-time requirements under the actual hardware constraints (concurrent access to data, number of cores). Both the real-time systems and the formal methods communities provide elegant techniques to realize such verification, which nevertheless face major challenges. For instance, model checking (formal methods) suffers from the state-space explosion problem, whereas schedulability analysis (real-time systems) is pessimistic and restricted to simple task models and schedulability properties. In this paper, we propose a scalable and generic approach to formally verify ERTSs. The core contribution is enabling, through joining the forces of both communities, compositional verification to tame the state-space size. To that end, we formalize a realistic ERTS model where tasks are complex with an arbitrary number of jobs and job segments, then show that compositional verification of such model is possible, using a hybrid approach (from both communities), under the state-of-the-art partitioned fixed-priority (P-FP) with limited preemption scheduling algorithm. The approach consists of the following steps, given the above ERTS model and scheduling algorithm. First, we compute fine-grained data sharing overheads for each job segment that reads or writes some data from the shared memory. Second, we generalize an algorithm that, aware of the data sharing overheads, computes an affinity (task-core allocation) guaranteeing the schedulability of hard-real-time (HRT) tasks. Third, we devise a timed automata (TA) model of the ERTS, that takes into account the affinity, the data sharing overheads and the scheduling algorithm, on which we demonstrate that various properties can be verified compositionally, i.e., on a subset of cores instead of the whole ERTS, therefore reducing the state-space size. In particular, we enable the scalable computation of tight worst-case response times (WCRTs) and other tight bounds separating events on different cores, thus overcoming the pessimism of schedulability analysis techniques. We fully automate our approach and show its benefits on three real-world complex ERTSs, namely two autonomous robots and an automotive case study from the WATERS 2017 industrial challenge.
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页数:21
相关论文
共 82 条
  • [1] Abdellatif T., 2010, Proceedings of the tenth ACM international conference on Embedded software, P229
  • [2] A Generic and Compositional Framework for Multicore Response Time Analysis
    Altmeyer, Sebastian
    Davis, Robert I.
    Indrusiak, Leandro
    Maiza, Claire
    Nelis, Vincent
    Reineke, Jan
    [J]. PROCEEDINGS OF THE 23RD INTERNATIONAL CONFERENCE ON REAL-TIME AND NETWORKS SYSTEMS (RTNS) 2015, 2015, : 129 - 138
  • [3] Alur R., 1999, Computer Aided Verification. 11th International Conference, CAV'99. Proceedings (Lecture Notes in Computer Science Vol.1633), P8
  • [4] MODEL-CHECKING IN DENSE REAL-TIME
    ALUR, R
    COURCOUBETIS, C
    DILL, D
    [J]. INFORMATION AND COMPUTATION, 1993, 104 (01) : 2 - 34
  • [5] Alur R, 2005, LECT NOTES COMPUT SC, V3576, P548
  • [6] Alur R., 1990, Proceedings. Fifth Annual IEEE Symposium on Logic in Computer Science (90CH2897-7), P414, DOI 10.1109/LICS.1990.113766
  • [7] ALUR R, 1992, LECT NOTES COMPUT SC, V600, P45, DOI 10.1007/BFb0031987
  • [8] Amnell T, 2003, LECT NOTES COMPUT SC, V2791, P60
  • [9] Bartocci Ezio, 2018, Lectures on Runtime. Verification Introductory and Advanced Topics. LNCS 10457, P1, DOI 10.1007/978-3-319-75632-5_1
  • [10] Techniques for multiprocessor global schedulability analysis
    Baruah, Sanjoy
    [J]. RTSS 2007: 28TH IEEE INTERNATIONAL REAL-TIME SYSTEMS SYMPOSIUM, PROCEEDINGS, 2007, : 119 - 128