Threshold voltage instability in SiO2-gate semi-vertical GaN trench MOSFETs grown on silicon substrate

We analyze the threshold voltage stability under positive gate stress in semi-vertical GaN trench MOSFETs with silicon oxide gate insulator. The experimental results, obtained by a fast setup capable of recording the threshold voltage transient with stress time as low as 10 mu s, indicate that positive gate voltage induces a trapping of electrons in oxide border traps. In addition, experimental data obtained at different temperature and recovery bias conditions suggest that trapping proceeds through tunneling, from the inversion channel in the p-GaN layer to the traps. Finally, we developed a mathematical framework to model such tunneling process that conceptually explains the origin of the strongly stretched trapping transients and the results were compared with some relevant references on positive bias temperature instability in Si and GaN based devices.