Optimized Design of a Variable Fractional Delay Filter With Delay Error Constraints

被引：2
|
作者：
Liu, Xiaowei [1 ]
Ren, Guangliang [1 ]
Zhang, Wenchao [1 ,2 ]
Liang, Shuang [1 ]
机构：
[1] Xidian Univ, State Key Lab Integrated Serv Networks, Xian 710071, Shaanxi, Peoples R China
[2] China Res Inst Radiowave Propagat, Natl Key Lab Electromagnet Environm, Qingdao 266107, Peoples R China
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2023年 / 70卷 / 08期
关键词：
Variable fractional delay (VFD); linear programming (LP); fractional delay error constraints (FDECs); BI-MINIMAX DESIGN; TRUE-TIME-DELAY; ARRAY;
D O I：
10.1109/TCSII.2023.3245723
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A novel algorithm for designing variable fractional delay (VFD) filter coefficients is proposed to improve time delay accuracy. The principle of this method is to model the coefficient design as an optimization problem with fractional delay error constraints (FDECs) and use a linear approach to derive a new FDEC expression for solving the problem. The solution of the FDEC expression can be efficiently obtained through linear programming (LP). Compared with existing algorithms, the design examples show the proposed method achieves a 100-fold improvement in delay accuracy while maintaining the frequency response (FR) error at an acceptable level, and yields a 5 dB reduction in FR error with the same level of delay accuracy.
引用
收藏
页码：3164 / 3168
页数：5
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