A Portable DSP Coprocessor Design Using RISC-V Packed-SIMD Instructions

This paper presents a portable coprocessor to accelerate digital signal processing (DSP) applications for low power Internet-of-Things (IoT) devices. The DSP coprocessor is based on RISC-V packed-SIMD instructions, and can be tightly integrated with various RISC-V cores as an independent IP by using an extension interface. The DSP coprocessor is verified on a Nexys A7 FPGA. The experimental method includes comparing the clock cycles of hamming codes, fast Fourier transforms (FFT) and digital filters running on the DSP coprocessor integrated with RISC-V cores and on original RISC-V cores. The results demonstrate a significant clock cycle reduction by up to 79.03%, 49.57% and 61.58%, respectively.