Analysis of the Impact of Interface Trap Charges on the Analog/RF Performance of a Graphene Nanoribbon Vertical Tunnel FET

One of the critical assessments in determining the functionality of a device is the issue of reliability in the context of the trap charges at the semiconductor and oxide interface. This article presents the results of a thorough investigation into the impact of interface trap charges (ITCs) on graphene-based channel double-gate dual-material gate graphene nanoribbon vertical tunnel field-effect transistors (DG-DMG-GNR-VTFETs). The proposed device, which takes into account GNR channel material, is compared to the conventional material, a silicon-based channel (DG-DMG-Si-VTFET), in the presence (positive/negative) or absence of trap charges, with the exact dimension specification. This work aims to assess the linearity of the proposed device and the dependability of devices with the influence of ITCs on the DC aspect, low power, and high-frequency parameters. Because of the special properties of graphene, it was found that the DG-DMG-GNR-VTFET performs better than the DG-DMG-Si-VTFET. The simulation in this work was performed using the Silvaco ATLAS TCAD device simulator.