GNRFET- and CNTFET-Based Designs of Highly Efficient 22 T Unbalanced Single-Trit Ternary Multiplier Cell

The internet-of-things and mobile devices have emerged as significant drivers in enhancing the living standards. As such devices rely on batteries, energy and area efficiency are top design priorities. For this purpose, one can consider using multiple-valued logic (MVL) and emerging low-power technologies. MVL enables using at least two logical values, thereby decreasing interconnections, area, and energy. Among MVL systems, ternary logic is regarded as the optimal subset when considering both complexity and cost. To design ternary circuits, multi-threshold (V-th) design approach is particularly well-suited. In light of this, graphene nanoribbon (GNR) and carbon nanotube (CNT) field-effect transistors (GNRFET and CNTFET) are supreme candidates. GNRFET and CNTFET devices benefit from the dependency of their V-th on GNR width and CNT diameter, correspondingly. This paper exploits the inherent capabilities of GNRFET and CNTFET devices to develop a highly efficient ternary multiplier (TMUL). The design leverages unary operators and dual-V-DD technique to dump binary/ternary logic gates and ternary circuits like decoder/encoder/multiplexer. To assess the proposed design efficiency, simulations are performed on Synopsis HSPICE simulator using 32-nm GNRFET and CNTFET technologies. The proposed TMUL has a significant decrease in transistor count, ranging from 4.35 to 15.38%. The CNTFET-based TMUL has up to 71.91%, 17.03%, and 76.35% improvements in delay, power, and energy, respectively. Meanwhile, the GNRFET-based TMUL has up to 63.55% improvement in power and 86.50% in energy. Moreover, employing GNRFET technology for implementing the proposed TMUL increases delay by 1.32 x while reducing power (energy) by 56.07% (42.92%) compared to CNTFET technology.