A Detailed Model of Cyclostationary Noise in Switched-Resistor Circuits

The Switched-Resistor (S-R) technique is becoming more and more interesting to implement low-voltage low-power active-RC filters with high tuning range and front-end amplifiers for biomedical circuits and systems. This approach exploits MOS switches driven by a duty-cycle-controlled clock signal to achieve tunability of the equivalent resistance and, hence, of the RC time constant. Since S-R circuits can be considered as linear periodically time variant (LPTV) systems with sampled outputs, we exploit the theory of the adjoint (inter-reciprocal) network in order to develop a detailed model of the cyclostationary noise involved in this kind of circuits. The proposed model allows to gain insight into the different noise sources and transfer functions involved, highlighting the circuit parameters on which the cyclostationary noise depends. Validation of the proposed model has been carried out by comparing analytical results against periodic noise simulations referring to a commercial 130nm CMOS process. The validation activity has confirmed the good accuracy of the proposed noise model and provided some useful design guidelines to optimize the noise performance of S-R circuits.