An Efficient VHDL Implementation of two Artificial Neural Networks on Zynq-7000 FPGA

被引：0

作者：

Sadeghikhah, Kaveh ^{[1
]}

Zhang, Lei ^{[1
]}

Paranjape, Raman ^{[1
]}

机构：

[1] Univ Regina, Engn & Appl Sci, Regina, SK, Canada

来源：

2023 IEEE CANADIAN CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING, CCECE | 2023年

关键词：

artificial neural network; FPGA; VHDL; training; activation function; MATLAB; weights; and biases;

D O I：

10.1109/CCECE58730.2023.10288905

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

This paper presents the FPGA implementation of two different topologies of an Artificial Neural Network (ANN) on the Xilinx Zynq-7000 evaluation board. The engine dataset available in MATLAB is used to train the neural network. The resulting parameters of a neural network are taken from MATLAB and are used to implement it on FPGA. Two structures are implemented with different accuracy of sfix_24_8 and sfix_32_16 and different clock frequencies and resource utilization is measured. The maximum achievable frequency measured is 83.33 MHz and the minimum power is 0.203 W.

引用

页数：6

共 9 条

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