Design and Simulation of Si and Ge Double-Gate Tunnel Field-Effect Transistors with High-κ Al2O3 Gate Dielectric: DC and RF Analysis

Steep subthreshold slope and high current on-off ratio are among the major challenges of tunnel field-effect transistors (TFETs) for low-power complementary metal-oxide-semiconductor (CMOS) device applications. This work presents the performance comparison of Si and Ge double-gate tunnel field-effecttransistors (DGTFETs) based on DC and RF analysis. As compared to Si-based DGTFET, the Ge-based DGTFET depicts an improved performance such as high ION of similar to 8.61 x 10(-5) A/mu m, low I-OFF of similar to 1.33 x 10(-12) A/mu m, I-ON/I(OFF )ratio of similar to 6.4 x 10(7 ), good sub-threshold swing of similar to 24.4 mV/dec, and better RF performance revealed from transconductance, parasitic capacitances, cut-off frequency, transit time, power delay product, and transconductance generation efficiency. Therefore, Ge-based TFET is a superior candidate for low-power CMOS device applications.