A Sub-<inline-formula> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula>W Energy-Performance-Aware IoT SoC With a Triple-Mode Power Management Unit for System Performance Scaling, Fast DVFS, and Energy Minimization

被引:3
作者
Liu, Xinjian [1 ]
Kamineni, Sumanth [1 ]
Breiholz, Jacob [1 ]
Calhoun, Benton H. [1 ]
Li, Shuo [2 ]
机构
[1] Univ Virginia, Dept Elect & Comp Engn, Charlottesville, VA 22903 USA
[2] Yale Univ, Dept Elect Engn, New Haven, CT 06511 USA
关键词
Phasor measurement units; Power demand; Internet of Things; Multitasking; Energy efficiency; Clocks; Task analysis; Buck converter; energy aware; fast dynamic voltage and frequency scaling (DVFS); high efficiency; Internet of Things (IoT); minimum energy point (MEP) tracking; performance aware; performance scaling; power management unit (PMU); sub-nW quiescent power; system-on-chip (SoC); wide dynamic range; OPERATION; CONVERTER; PROCESSOR;
D O I
10.1109/JSSC.2024.3350449
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This article presents an ultra-low-power (ULP) Internet-of-Things (IoT) system-on-chip (SoC) using a triple-mode power management unit (PMU) to achieve self-adaptive power-performance scaling and energy-minimized operation. The proposed PMU comprises three modes: energy-aware (EA) mode, performance-aware (PA) mode, and minimum energy point (MEP) tracking mode. By controlling a microprocessor with the three modes, the SoC can adaptively scale its frequency and supply voltage based on either the input energy availability or the task priority. To achieve robust and rapid mode transitions, the SoC adopts fast dynamic voltage and frequency scaling (DVFS) and fast load transient response (FLTR) through asynchronous control. For energy-minimized operation, a sub-nW constant-energy-cycle (CEC) algorithm keeps the microprocessor operating at the MEP with a 0.026-mm(2) area overhead. In addition, the on-chip integration of a bias generator (BG), clock (CLK), and power-on-reset block empowers the SoC to be a fully self-contained system. Fabricated in 65-nm CMOS, measurement results show that the SoC has a minimum power consumption of 194.3 nW at 180 Hz. The proposed PMU achieves 5.2-nW quiescent power and 92.6% peak efficiency while maintaining > 80% efficiency from 190 nW to 3 mW. The MEP tracking (MEPT) circuits achieve < 2.3% energy per cycle error and < 18 mV voltage tracking error. The measured quiescent power of the MEPT circuits in the idle mode is 379 pW, which only accounts for 0.19% of the total system power. Measurements of the triple-mode transitions show that this SoC is well suited for resource-constrained IoT applications.
引用
收藏
页码:2272 / 2285
页数:14
相关论文
共 32 条
  • [1] Amin SS, 2018, ISSCC DIG TECH PAP I, P144, DOI 10.1109/ISSCC.2018.8310225
  • [2] [Anonymous], CR2032 COIN BATT DAT
  • [3] Art S., 2016, EE J CHALK TALK SER
  • [4] Asanovi K., 2016, Tech. Rep. UCB/EECS-2016-17
  • [5] A dynamic voltage scaled microprocessor system
    Burd, TD
    Pering, TA
    Stratakos, AJ
    Brodersen, RW
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2000, 35 (11) : 1571 - 1580
  • [6] Modeling and sizing for minimum energy operation in subthreshold circuits
    Calhoun, BH
    Wang, A
    Chandrakasan, A
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (09) : 1778 - 1786
  • [7] A 2.4 GHz-91.5 dBm Sensitivity Within-Packet Duty-Cycled Wake-Up Receiver
    Dissanayake, Anjana
    Bishop, Henry L.
    Bowers, Steven M.
    Calhoun, Benton H.
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2022, 57 (03) : 917 - 931
  • [8] github, RISC V OPENOCD OFFIC
  • [9] Kamineni S., 2023, THESIS U VIRGINIA CH
  • [10] Kang JG, 2018, ISSCC DIG TECH PAP I, P424, DOI 10.1109/ISSCC.2018.8310365