Ising machines have shown great promise in solving combinatorial optimization problems (COPs) using nature-inspired computation with higher speed and efficiency over traditional von Neumann computing systems. CMOS-based implementations combine the maturity and scaling ability of CMOS with the efficacy of Ising machines. In this paper, a low-density parity-check (LDPC) decoding solution is implemented with a CMOS-based resistively-coupled Ising machine known as(QuBRIM), using multi-body interactions among CMOS-based Ising machine nodes for the first time. State-of-the-art CMOS-based Ising implementations currently utilize order reduction to solve problems with higher-than-quadratic terms. In this paper, a new mechanism is proposed to implement higher-than-quadratic terms on Ising machines without the need for order reduction. The proposed methodology is implemented and verified with CMOS technology using 45 nm Generic PDK (GPDK).High accuracy rates are reported for the LDPC decoder based on the proposed methodology, comparable to Normalized Min-Sum, Offset Min-Sum, and Layered Belief-Propagation decoders, with a bit error rate (BER) as low as 4x10(-8) at a signal-to-noise ratio(SNR) of 4dB. Furthermore, the proposed LDPC decoder attains a normalized energy efficiency (NEE) of 1.29 pJ/bit/iteration, surpassing the state-of-the-art decoders by a minimum factor of2.4 and as much as 7.6 times.