Analytical Modeling and Simulation of a Triple-Material Double-Gate SON TFET with Stacked Front-Gate Oxide for Low-Power Applications

This paper proposes a two-dimensional analytical model of a triple-material double-gate silicon-on-nothing tunnel field-effect transistor (TM-DG SON TFET) with stacked front-gate oxide. The front-gate dielectric consists of both high-kappa and low-kappa dielectric layers to form high ON current and low OFF current, whereas air is used in the back gate to suppress ambipolar behavior. To achieve high ON current, tunneling barrier width between source and channel is modulated using different ratios of three gate metal lengths. Moreover, the analytical model of the surface potential inside the channel is derived by solving the two-dimensional Poisson's equation using parabolic approximation. Finally, drain current is analytically derived by integrating band to band generation rate over the tunnel volume, using the minimum and maximum tunneling paths.