High isolation and high power of 0.13 μm CMOS SPDT switch using deep-N-well transistors and floating-body technique in K-band

被引：2

作者：

Wang, Zongxiang ^{[1
,3
]}

Cheng, Guoxiao ^{[2
]}

Kang, Wei ^{[2
]}

Li, Zekun ^{[1
]}

Chen, Jixin ^{[1
]}

机构：

[1] Southeast Univ, Sch Informat Sci & Engn, State Key Lab Millimeter Waves, Nanjing, Peoples R China

[2] Nanjing Univ Sci & Technol, Ministerial Key Lab JGMT, Nanjing, Peoples R China

[3] Southeast Univ, Sch Informat Sci & Engn, State Key Lab Millimeter Waves, Nanjing 210096, Peoples R China

来源：

MICROWAVE AND OPTICAL TECHNOLOGY LETTERS | 2023年 / 65卷 / 08期

关键词：

CMOS SPDT; deep-N-well; floating-body; high isolation; K-band; DESIGN;

D O I：

10.1002/mop.33671

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A K-band high isolation single-pole double-throw (SPDT) switch using a 0.13 mu m CMOS process is presented. Two on-state resistors of shunt Deep-N-Well (DNW) transistors are used to improve isolation. The floating-body technique is utilized to enhance the power-handling capability. The off-state capacitors of two DNW transistors are employed to construct an impedance-matching network. The switch achieves a measured insertion loss of 3.0-3.2 dB and an isolation of better than 35 dB from 17 to 27 GHz. A measured input 1 dB compression power (IP1dB) of 11.8 dBm is obtained at 24 GHz. The chip size of the proposed switch is 0.52 x 0.66 mm(2) with a core area of only 0.33 x 0.27 mm(2).

引用

页码：2126 / 2131

页数：6

共 28 条

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