IEC ESD Co-Design Methodology for On-Chip Protection at High Voltage Fault Tolerant Transceivers

被引：0
|
作者：
Kontos, Dimitrios [1 ]
Chen, Wensong [1 ]
Vashchenko, Vladislav [1 ]
机构：
[1] Analog Devices Inc, 130 Rio Robles, San Jose, CA 95134 USA
来源：
2023 45TH ANNUAL EOS/ESD SYMPOSIUM, EOS/ESD | 2023年
关键词：
D O I：
10.23919/EOS/ESD58195.2023.10287750
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
System Level ESD and Fault protection co-design approach on high voltage tolerant transceivers is presented. Two-stage protection network is defined for the case of +/- 65V CANL output stage. Methodology incorporates dual-directional SCR overshoot at triggering, calculation of parameters for the fault protection snubber clamp and internal circuit pulsed SOA limits.
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页数：8
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