IEC ESD Co-Design Methodology for On-Chip Protection at High Voltage Fault Tolerant Transceivers

被引：0
|
作者：
Kontos, Dimitrios [1 ]
Chen, Wensong [1 ]
Vashchenko, Vladislav [1 ]
机构：
[1] Analog Devices Inc, 130 Rio Robles, San Jose, CA 95134 USA
来源：
2023 45TH ANNUAL EOS/ESD SYMPOSIUM, EOS/ESD | 2023年
关键词：
D O I：
10.23919/EOS/ESD58195.2023.10287750
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
System Level ESD and Fault protection co-design approach on high voltage tolerant transceivers is presented. Two-stage protection network is defined for the case of +/- 65V CANL output stage. Methodology incorporates dual-directional SCR overshoot at triggering, calculation of parameters for the fault protection snubber clamp and internal circuit pulsed SOA limits.
引用
收藏
页数：8
相关论文
共 50 条
  • [1] High voltage tolerant on-chip ESD protection in low-voltage BiCMOS process
    Vashchenko, VA
    Kindt, W
    Hopper, P
    JOURNAL OF ELECTROSTATICS, 2006, 64 (02) : 104 - 111
  • [2] System ESD robustness by co-design of on-chip and on-board protection measures
    Gossner, H.
    Simbuerger, W.
    Stecher, M.
    MICROELECTRONICS RELIABILITY, 2010, 50 (9-11) : 1359 - 1366
  • [3] ESD protection design with on-chip ESD bus and high-voltage-tolerant ESD clamp circuit for mixed-voltage I/O buffers
    Ker, Ming-Dou
    Chang, Wei-Jen
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2008, 55 (06) : 1409 - 1416
  • [4] ESD Optimization with On-chip and On-board Co-design ESD Protection Strategy for Mixed Signal System in Package
    Huang Xiaozong
    Liu Zhiwei
    Liu Fan
    Cheng Hui
    Liou, J. J.
    7TH IEEE INTERNATIONAL NANOELECTRONICS CONFERENCE (INEC) 2016, 2016,
  • [5] A novel co-design and evaluation methodology for ESD protection in RFIC
    Li, Li
    Liu, Hongxia
    Yang, Zhaonian
    Chen, Linlin
    MICROELECTRONICS RELIABILITY, 2012, 52 (11) : 2632 - 2639
  • [6] An on-chip NMOS ESD protection circuit with low trigger voltage and high ESD robustness
    Chen, Di-Ping
    Liu, Xing
    He, Long
    Chen, Si-Yuan
    Hunan Daxue Xuebao/Journal of Hunan University Natural Sciences, 2 (115-118):
  • [7] A new design for complete on-chip ESD protection
    Wang, AZ
    PROCEEDINGS OF THE IEEE 2000 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2000, : 87 - 90
  • [8] On the design of tunable high-holding-voltage LVTSCR-based cells for on-chip ESD protection
    Salcedo, JA
    Liou, JJ
    Bernier, JC
    2004: 7TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUITS TECHNOLOGY, VOLS 1- 3, PROCEEDINGS, 2004, : 798 - 803
  • [9] Double snapback characte'ristics in high-voltage nMOSFETs and the impact to on-chip ESD protection design
    Ker, MD
    Lin, KH
    IEEE ELECTRON DEVICE LETTERS, 2004, 25 (09) : 640 - 642
  • [10] High performance SCR's for on-chip ESD protection in high voltage BCD processes
    Vashchenko, VA
    Concannon, A
    ter Beek, M
    Hopper, P
    ISPSD'03: 2003 IEEE 15TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS PROCEEDINGS, 2003, : 261 - 264
12345