A Power-Efficient Level-Crossing Analog-to-Digital Converter with Adaptive Resolution Based on a Signal-Dependent Sampling Mechanism

In this paper, a level-crossing analog-to-digital converter (LC-ADC) with the adaptive resolution is proposed which utilizes a signal-dependent sampling mechanism to adjust the quantization levels. Using a feedback network, composed of a charge-pump and a comparator, the periodicity of the samples is continuously evaluated. The quantization window is then dynamically configured according to the signal activity to prevent excessive sampling of the input signal, especially for the parts with relatively high slew rates. As a result, by regulating the number of samples, the design of the ADC main building blocks is relaxed regarding the speed and power requirements leading to higher power efficiency. Implemented in a 0.18 mu m standard CMOS process, the proposed LC-ADC occupies similar to 0.0041 mm(2) of silicon area and consumes similar to 18 nW from 1 V supply voltage. Assuming a 1 kHz full-scale input sinusoidal signal, it achieves an average signal-to-noise and distortion ratio of similar to 43 dB and an effective number of bits of similar to 6.8 bits.