Design and implementation of hardware-efficient architecture for saturation-based image dehazing algorithm

被引:7
作者
George, Anuja [1 ]
Jayakumar, E. P. [1 ]
机构
[1] Natl Inst Technol Calicut, Dept Elect & Commun Engn, Kozhikode, Kerala, India
关键词
Image dehazing; Saturation; Transmission map; Real-time processing; Sensor nodes; Hardware Architecture; HAZE REMOVAL; VISIBILITY;
D O I
10.1007/s11554-023-01356-x
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
For real-time single-image dehazing, this paper suggests a straightforward and efficient saturation-based transmission map estimation method. For the suggested image dehazing algorithm, the design of a hardware-efficient very large scale integration (VLSI) architecture is also provided. By removing the computationally demanding sorting operations, the algorithm computes the dark channel, increases the robustness of atmospheric light estimation using a hardware-friendly local atmospheric light estimation module based on the pixel saturation values, and reduces the effects of halo artifacts using an edge-preserving filter to estimate the saturation-based transmission map. Compared to previous sophisticated dehazing approaches, this study exhibits competitive performance in the quality of the dehazed images. The best of the existing dehazing architecture as well as the proposed architecture are described in Verilog hardware description language (HDL), functionally verified using Vivado 2019.1 simulator, and synthesized using Cadence genus compiler. The results of the implementation show that the suggested design is hardware-efficient and offers higher throughput. The suggested dehazing architecture achieves better results in terms of area and delay than the most recent methods and is appropriate for applications with hardware restrictions.
引用
收藏
页数:11
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