Design and realization of area-efficient approximate multiplier structures for

The multiplier is a vital element in real-time applications. This work intends to build area-efficient multipliers based on the approximation concept. The approximate computing scheme receives considerable attention generally in error-resilient applications like image processing which reduce the design parameters at the expense of slightly sacrificing the precision of the performance. This paper proposes the two approximate multipliers (PAM-1 & PAM-2) using the modified 4:2 compressor, full-adder, and sum generation component. The main essence of the proposed approximate multiplier structures is to divide the partial product generation rows into (n/2) stages. The proposed approximate compressors are employed to compress partial products on the LSB side of the multiplier, while accurate compressors are utilized on the MSB side. By effectively combining approximate and exact compressors, the developed approximate multipliers achieve better results in terms of circuit parameters and acceptable error metrics compared to existing imprecise designs. These improvements are reflected in the implementation tables reported in the paper. Compared with the accurate multiplier, the proposed multiplier (PAM-2) reduce the area requirement, delay and power consumption by 38%, 46%, and 50%, respectively. In addition, while extending to image processing applications like multiplication, smoothing, and sharpening, the proposed approximate multipliers attain a better image quality than existing designs, which measure in terms of the mean structural similarity index metric.