Multi-state tunnel field effect transistor based on face tunneling with gate-source overlap

被引:1
作者
Sun, Jiale [1 ]
Zhang, Yuming [1 ]
Lv, Hongliang [1 ]
Lyu, Zhijun [2 ]
Lu, Bin [3 ]
Zhu, Yi [1 ]
Pan, Yuche [1 ]
机构
[1] Xidian Univ, Key Lab Wide Band Gap Semicond Mat & Devices, Xian 710071, Peoples R China
[2] Inst Microelect Technol, Dept Integrated Circuit Design, Xian 710004, Peoples R China
[3] Shanxi Normal Univ, Sch Phys & Informat Engn, Taiyuan 030031, Peoples R China
基金
中国国家自然科学基金;
关键词
Ternary logic; Tunnel Field Effect Transistor (TFET); Band to Band Tunneling (BTBT); Surface tunneling; LOGIC; CMOS;
D O I
10.1016/j.sse.2023.108593
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, a ternary surface tunneling field effect transistor (TF-TFET) based on the tunneling mechanism is designed and fabricated. By adjusting the parameters and bias voltage of the surface tunneling and the line tunneling, the transistor introduces a stable "intermediate state" between the switching states of conventional binary TFET devices, which realizes the function of a ternary logic device. The device can realize the conversion of ternary logic and binary logic devices under certain conditions, and realize various functions. The fabrication process of the device is compatible with the traditional CMOS process and is also of great significance for realizing the development of the ternary logic operation unit.
引用
收藏
页数:6
相关论文
共 50 条
[41]   Characterization and modeling of dual material double gate tunnel field effect transistor using superposition approximation method [J].
Jossy, A. Maria ;
Vigneswaran, T. ;
Malarvizhi, S. ;
Nagarajan, K. K. .
CONCURRENCY AND COMPUTATION-PRACTICE & EXPERIENCE, 2019, 31 (14)
[42]   Design and simulation of triple metal double-gate germanium on insulator vertical tunnel field effect transistor [J].
Chawla, Tulika ;
Khosla, Mamta ;
Raj, Balwinder .
MICROELECTRONICS JOURNAL, 2021, 114
[43]   Analog and linearity performance analysis of ferroelectric vertical tunnel field effect transistor with and without source pocket [J].
Singh, Ashish Kumar ;
Kumar, Ramesh ;
Maity, Heranmoy ;
Singh, Prabhat ;
Singh, Sarabdeep .
INTERNATIONAL JOURNAL OF NUMERICAL MODELLING-ELECTRONIC NETWORKS DEVICES AND FIELDS, 2024, 37 (04)
[44]   Impact of source height on the characteristic of U-shaped channel tunnel field-effect transistor [J].
Yang, Zhaonian ;
Zhang, Yue ;
Yang, Yuan ;
Yu, Ningmei .
SUPERLATTICES AND MICROSTRUCTURES, 2017, 111 :1226-1232
[45]   A T-shaped gate tunneling field effect transistor with negative capacitance, super-steep subthreshold swing [J].
Li, Wei ;
Jia, Qingrui ;
Pan, Yumei ;
Chen, Xi'an ;
Yin, Yue ;
Wu, Yupan ;
Wang, Yucheng ;
Wen, Yi ;
Wang, Chao ;
Wang, Shaoxi .
NANOTECHNOLOGY, 2021, 32 (39)
[46]   Reconfigurable Double Gate Carbon Nanotube Field Effect Transistor Based Nanoelectronic Architecture [J].
Liu, Bao .
PROCEEDINGS OF THE ASP-DAC 2009: ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 2009, 2009, :853-858
[47]   Ultrasensitive Gas Nanosensor Based on Doping-less Carbon Nanotube Tunnel Field-Effect Transistor with a Sensitive Drain-Gate [J].
Tamersit, Khalil ;
Bourouba, Hocine .
2024 IEEE WORKSHOP ON COMPLEXITY IN ENGINEERING, COMPENG 2024, 2024,
[48]   Optimization of Tunnel Field-Effect Transistor-Based ESD Protection Network [J].
Zhu, Zhihua ;
Yang, Zhaonian ;
Fan, Xiaomei ;
Zhang, Yingtao ;
Liou, Juin Jei ;
Fan, Wenbing .
CRYSTALS, 2021, 11 (02) :1-11
[49]   Analytical Modeling and Simulation of Dual Material Double Gate All Around Tunnel Field Effect Transistor using MATLAB [J].
Bharathi, Helen Ramya R. ;
Karthikeyan, P. .
2017 INTERNATIONAL CONFERENCE ON INNOVATIONS IN INFORMATION, EMBEDDED AND COMMUNICATION SYSTEMS (ICIIECS), 2017,
[50]   Ultra Thin Body Single Gate Nanoscale Dopingless Si:Ge Heterostructure Junctionless Tunnel Field Effect Transistor [J].
Asthana, Pranav Kumar ;
Pal, Brij Kishor ;
Goswami, Yogesh ;
Basak, Shibir ;
Ghosh, Bahniman .
JOURNAL OF ADVANCED PHYSICS, 2014, 3 (03) :205-208