The Role of Interface Trap States in MoS2-FET Performance: A Full Quantum Mechanical Simulation Study

As the fabrication of short-channel MoS2- FET has made significant progress, there is a growing need to understand the factors affecting the transfer characteristics for overcoming the variability issue. Even though several experimental works on the MoS2-oxide interfaces have reported the presence of high-density interface trap charge, insight into the device-level perfor-mance degradation is still unexplored. To address this gap, we introduce the description of the interface trap states in the self-consistent solutions of 2-D Poisson's equation and dissipative nonequilibrium Green's function (NEGF) by modifying the on-site potential energy in the atomic description of the channel. Our results indicate that inter-face trap states with energy toward the mid-gap energy level from the conduction band significantly increase the OFF-state current due to phonon-assisted source-drain tun-neling current with trap states, while the charge trapping in the interface states reduces the ON-state current. It is found that the interface trap states close to the mid-gap severely affect the key device performance metrics, such as OFF-state current (I-OFF), subthreshold slope (SS), and threshold voltage (V-TH), for the sub-18 nm gate length. Additionally, the inelastic tunneling through trap states marginally enhances the temperature dependency in SS and V-TH of MoS2-FET. The simulation results suggest that minimizing the interface trap states with energy close to mid-gap energy level and trap position around the middle of the channel can considerably reduce the leakage current and improve the short-channel MoS2-FET performance.